This iambic keyer core is written in Verilog and is designed to be a drop-in component of any FPGA-based ham radio project. The core has been tested on an Actel MicroSemi ProASIC3 FPGA, but is written in portable Verilog RTL and should synthesize readily on any other architecture.
Files
Features
- Supports both Mode A and Mode B keying, selected by an input to the module.
- Dot and dash insertion.
- Keying speed input.
- User-interface features like setting the speed, selecting the mode, and swapping paddles are left up to you.
- Top level module and physical constraints file provided for stand-alone operation.
- Testbench included.
- Short and simple, but thoroughly commented.
- Tested in hardware on an Actel A3PN250Z.
The core is released under the GNU General Public License version 3.
Posts
- Iambic keyer in Verilog (2011-06-15)
- The iambic keyer core is alive (2011-06-20)
- A Morse code keyer in VHDL (2011-08-05)
Thank you, I am merging your keyer with the Cypress PSOC3 chip on the Omnia Basic aka Peaberry SDR for a standalone CW transmitting, and it seem to work.
Glad to hear you’re finding it useful!