A Morse code keyer in VHDL

I found another FPGA Morse code keyer project! This one is written in VHDL by Jim Brady. He has posted the source (for a Xilinx Spartan 3A).  He also posted his vintage keyer designs from the 1960’s and 1970’s.

Jim’s design is not iambic, but does have dot and dash memory. Speed adjustment is done via an RS-232 serial link to a PC.

If VHDL is your hardware language of choice, or if just would like another take on Morse keying, Jim’s keyer is worth a look.  Of course, if you’re interested in a small iambic keyer core in Verilog, have a look at the skywired.net iambic keyer.

Update 8/8/11: Jim tipped me off to another VHDL keyer published online. This one is designed for a Cypress CPLD and is written in VHDL. It’s on pages 53-73 of Circuits I Have Known, by Ronald W. Parker. A PDF is available at controlsignalconverter.com, and the book itself is available at Amazon.