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Tag Archives: iambic
Humbled by a sine wave oscillator
The old saw goes, “oscillators don’t, amplifiers do”, but that’s an analog saying. It doesn’t apply to the digital world. After all, digital is easy, while analog is hard, right? (Be careful not to answer too quickly!) For the last … Continue reading
Posted in Design Notes, Projects
Tagged Agile, delta-sigma, design, FPGA, iambic, keyer, sine wave, test-driven development, theory
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A Morse code keyer in VHDL
I found another FPGA Morse code keyer project! This one is written in VHDL by Jim Brady. He has posted the source (for a Xilinx Spartan 3A). He also posted his vintage keyer designs from the 1960′s and 1970′s. Jim’s … Continue reading
The iambic keyer core is alive
With just a few tweaks, I brought up the “IambicV” iambic keyer core on one of my A3PN250 breakout boards. I was stunned when it made dits, dahs, and iambic dah-dits perfectly the first time out. Yes, I know that’s what a testbench is supposed to make possible, and yes, I’ve had it happen before, but I still always expect smoke the first time I turn something on.
I made a few changes from last week’s version. Continue reading
Iambic keyer in Verilog
If my goal is to build an FPGA-based ham radio, one of the modules I can’t do without is an iambic keyer. I have to confess that I have never been much of a CW (Morse code) operator, but with so many logic gates available, it would be a shame to leave out a keyer.
Writing an iambic keyer turned out to be a good way to get the kinks out of the FPGA toolchain. The code itself is pretty simple and straightforward. One flip-flop keeps track of whether the current symbol is a dit or a dah. Another tracks whether the paddle for the opposite symbol (dah or dit, respectively) has been pressed during the current symbol. Finally, a two-level counter handles the timing of the dits and dahs and operates the key line. There is a simple sidetone, too. Continue reading
