The FPGA level shifter: not entirely crazy!

Some months ago, I came across an Actel app note that advocated using FPGAs as level shifters. “What a crazy waste of computing power,” I thought to myself, “though I suppose they are just trying to sell the low-end ProASIC3 nano FPGAs.” With that, I set the thought aside.

Much later, I ran into a problem.

Some months ago, I came across an Actel app note that advocated using FPGAs as level shifters. “What a crazy waste of computing power,” I thought to myself, “though I suppose they are just trying to sell the low-end ProASIC3 nano FPGAs.”  With that, I set the thought aside.

Much later, I ran into a problem. I had a prototype board to design. It had to plug into an existing, quite complicated microprocessor evaluation kit, adding a data radio and a few other functions to the system. After poring over the schematic for hours, the software developer, who I’ll call S, and I still weren’t 100% sure which pins on the expansion bus were free for our use, though we had a long list of pins that definitely were not suitable. On top of that, I had a level-shifting problem. The evaluation kit ran at 1.8 V and 2.75 V, with signals at both levels on the bus, but the radio required 3.3 V logic levels. Continue reading “The FPGA level shifter: not entirely crazy!”