Some months ago, I came across an Actel app note that advocated using FPGAs as level shifters. “What a crazy waste of computing power,” I thought to myself, “though I suppose they are just trying to sell the low-end ProASIC3 nano FPGAs.” With that, I set the thought aside.
Much later, I ran into a problem. I had a prototype board to design. It had to plug into an existing, quite complicated microprocessor evaluation kit, adding a data radio and a few other functions to the system. After poring over the schematic for hours, the software developer, who I’ll call S, and I still weren’t 100% sure which pins on the expansion bus were free for our use, though we had a long list of pins that definitely were not suitable. On top of that, I had a level-shifting problem. The evaluation kit ran at 1.8 V and 2.75 V, with signals at both levels on the bus, but the radio required 3.3 V logic levels.
That Actel app note came to mind, and I thought, “I wonder what is the cheapest ProASIC3 with three I/O banks?” Three I/O banks were needed because each bank has an independent power supply, so I would run one bank at 1.8V, one at 2.75 V, and one at 3.3 V. I found the A3PN015, a 15,000 gate (nominal) FPGA. I designed the board to run all of the possibly-available pins of the expansion bus to I/O banks wired at 1.8 V and 2.75 V, and all of the signals to the radio out an I/O bank wired at 3.3 V. The radio’s power supply had an enable pin on it, too, which I ran to the FPGA even though S assured me it would never be powered down. I would program the enable to be a constant “1”.
Once the boards arrived, I worked with S to find the right configuration of pins. It took us four tries to get right, so my unease about our tracing of the schematic was deserved. After ruling out the pins that were not actually available or unusable, we were using every free pin.
Two days later came the request: Could I make the radio’s power supply switchable? Turning the radio off and on turned out to be essential for resetting it. I patted myself on the back for running that enable line to the FPGA. With a little thought, S and I identified a combination of signals that would never be used in normal operation. I put a little glue logic into the FPGA to use that combination to enable the power supply, and we were set.
I learned a few lessons from this escapade. First, being able to reroute signals by reprogramming the FPGA was enormously useful. Without that capability, the board would have been covered with little ECO wires. Second, although I had planned to waste all of the logic resources of the FPGA, using it only for level shifting, it was very convenient to have it when I needed glue logic. Again, it saved me from having to wire something in with little blue wires.
Finally, I reflected a bit on the cost. I needed to level-shift 13 lines. The FPGA cost $4.71 (qty 1). If I had used four SN74AVC4T774‘s, my favorite level shifter for complex situations like this, it would have cost $4.64. ($1.16 qty 1). The FPGA also needed a JTAG header and more decoupling caps than the ‘4T774s would, though the latter would have needed a few chips of glue logic. The price ends up being more or less a wash. The FPGA prevented a lot of ECO wires, though, so labor savings more than makes up the difference. I have to admit that for production quantities, I still might be better off with standard-logic parts, but the decision is not as clear-cut as it once was.
After all this, I went back and re-read the app note. It turns out that it was about level-shifting with unused pins on an FPGA that was already in-system. Oops! That idea is nowhere near as crazy as using an entire FPGA solely for level-shifting. In fact, it’s smart. A dedicated level-shifting FPGA doesn’t seem as crazy any more, either.
What do you think? Is it nuts to use an FPGA as a level shifter?